1. Field of the Invention
This invention relates in general to the field of instruction execution in computer systems, and more particularly to a method and apparatus for reducing the number of instruction cycles that are required to perform a read from a flags register in a pipeline microprocessor.
2. Description of the Related Art
In an x86 pipeline microprocessor, instructions that perform a write to the EFLAGS register (e.g., POPF/POPFD, CLI/STI, CLD/STD, CLC/STC) take a significant number of cycles to execute. This is because writes to the EFLAGS register are conditioned upon the current I/O privilege level (IOPL) and the state of certain bits within the EFLAGS register at the time of a write. Under the Microsoft Windows® operating system, upon each return from a called subroutine the EFLAGS register is popped off of the stack, thus causing a notable operating system delay.
Therefore, what is needed is a technique for operating a microprocessor that reduces the delay associated with instructions that perform a write to the EFLAGS register, such as pop instructions, for example.
It is also observed that in an x86 pipeline microprocessor, a push of the EFLAGS register (i.e., PUSHF/PUSHFD) on to the stack takes a significant number of cycles. This is because the state of the bits that are read from the EFLAGS register and the execution state of the processor are conditioned upon the current I/O privilege level (IOPL) and the state of particular bits within the EFLAGS register at the time of a push. Each call to a subroutine in the Microsoft Windows® operating system causes the EFLAGS register to be pushed to the stack, thus causing a notable operating system delay.
Thus, what is needed is a technique for operating a microprocessor that reduces the delay associated with performing EFLAGS stack pushes which perform a read from EFLAGS.